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Generated imageDesign & EDA

Cadence's Amol Borkar explains why AI voice at the edge demands a rethink of SoC architecture, not just faster processors

Semiconductor Engineering's interview with Cadence's Tensilica DSP lead lays out why NLP is reshaping audio SoC design - and why raw clock speed is the wrong lever to pull.

10 Sept 2026Generated imageDesign & EDA

French gendarmerie researchers show voltage glitching bypasses eMMC password locks on 3 of 10 commercial parts, with measurable evidence alteration

A paper from France's Institut de Recherche Criminelle quantifies both the success rate and the data-integrity cost of fault-assisted eMMC access in forensic investigations.

10 Sept 2026Generated imageSemiconductors

Cadence's Tensilica HiFi iQ DSP puts natural language processing directly on edge SoCs

Cadence's sixth-generation Tensilica HiFi iQ DSP delivers 2x compute and 8x AI performance over its predecessor, moving NLP and voice AI fully on-device for edge SoCs.

10 Sept 2026Generated imageSemiconductors

Keysight's forensic team argues hardware-layer testing is now a prerequisite for locked-device investigations

Keysight Device Security Testing published a framework in August 2026 explaining when and how forensic teams must move beyond software acquisition into side-channel analysis and fault injection.

10 Sept 2026Generated imageDesign & EDA

NVIDIA details Vera CPU's Olympus core architecture at Hot Chips 2026, claiming 1.8x agentic AI speedup

NVIDIA presented the full microarchitecture of its 88-core Vera CPU at Hot Chips 2026 on 24 August, claiming up to 1.8x faster task completion on agentic workloads versus x86 competitors.

9 Sept 2026Generated imageDesign & EDA

Chips&Media's WAVE6331X FuSa video codec IP earns ISO 26262 ASIL-B certification from DNV

Chips&Media received ISO 26262 ASIL-B certification for its WAVE6331X FuSa video codec IP on 2 September 2026, covering H.264, H.265, AV1, and VP9 for automotive SoC integration.

9 Sept 2026Generated imageSemiconductors

SEMI publishes nine-point position paper urging EU to widen Chips Act 2.0 beyond fabs

SEMI has published a nine-recommendation position paper calling on EU co-legislators to extend Chips Act 2.0 incentives across the full semiconductor value chain, from design to advanced packaging.

9 Sept 2026Generated imageSemiconductors

Energy Vault completes land acquisition for its 125 MW / 1 GWh Stoney Creek BESS in New South Wales

Energy Vault has acquired full freehold ownership of the Stoney Creek BESS site in northern NSW, clearing a key development hurdle ahead of a Q1 2027 construction start.

9 Sept 2026Generated imageSemiconductors

Humanoid robot shipments surged nearly 300% in H1 2026, but battery life and compute architecture remain the hard limits

Global humanoid robot shipments exceeded 22,000 units in H1 2026, up nearly 300% year-on-year. The semiconductor industry is now the binding constraint on how fast the ramp can continue.

9 Sept 2026Generated imageSemiconductors

SEMI and Silicon Catalyst sign global MOU to connect semiconductor startups with industry networks

SEMI and Silicon Catalyst signed a global MOU at SEMICON Taiwan 2026 on 2 September, linking the accelerator's 150+ portfolio companies with SEMI's 4,000-member global network.

8 Sept 2026Generated imageDesign & EDA

AI is compressing the design cycle - and exposing physical realization as the next bottleneck

As agentic AI shrinks the path to tape-out, the constraint in semiconductor development is migrating downstream - into packaging, multi-physics signoff, and physical realization.

8 Sept 2026Generated imageDesign & EDA

Synopsys hosts TetraMem and ANAFLASH at DAC 2026 to show compute-in-memory chips attacking the AI weight-movement bottleneck

At DAC 2026 on 28 July, Synopsys hosted TetraMem and ANAFLASH to show how non-volatile compute-in-memory chips sidestep the data-movement cost that limits AI at the edge.

8 Sept 2026